Dual-node capacitor coupled MOSFET for improving ESD performance

ABSTRACT

A dual-node capacitor coupling technique is used to lower the trigger voltage and to improve the uniform turn-on of a multi-finger MOSFET transistor. Preferably, each MOSFET is an NMOS device. Specifically, each NMOS device includes a capacitor that is connected between the gate of the NMOS device and the pad terminal. A first resistor is connected between the gate and the p-well, while a second resistor is connected between the p-well and the grounded source. For a positive ESD pulse to VSS, the p-well is pulled up to approximately 0.7 V during the initial ESD event, such that the source junction is forward biased and that the trigger voltage of the NMOS device is lowered. At the same time the gate voltage is coupled within the range of approximately 1 to 2 V to promote the uniform turn on of the gate fingers of the NMOS devices during the initial ESD event.

FIELD OF THE INVENTION

The present invention relates to a primary ESD protection circuit, andmore particularly, the present invention relates to a primary ESDprotection circuit having a dual-node capacitor coupled multi-fingerNMOSFET structure.

BACKGROUND OF THE INVENTION

Electrostatic discharges (ESDs) from human handling of a metal-oxidesemiconductor (MOS) IC chip, or from other causes, permanently damagethe IC chip. Often the thin-oxide layer that isolates the gate electrodefrom the substrate of a MOS field effect transistor is irreparablyruptured by a voltage spike applied across it. A voltage spike or ESD isoften applied to the gate, because the gate electrode is connected to anexternal terminal or pin of the IC chip. The external terminals areformed on an input or output pad. To prevent such damage from excessiveelectrostatic discharges, a protective device is often connected betweenthe pad and the internal circuits.

As CMOS technology is scaled down into submicron regime, the processesand the structures, such as a thinner gate oxide, shorter channellength, shallower source/drain junction, LDD (Lightly-Doped Drain)structure, and silicided diffusion, greatly degrade the ESD robustnessof submicron CMOS ICs. Submicron CMOS devices, such as short channelthin-oxide MOS devices, are extremely susceptible to ESD damage.Therefore, ESD protection has become one of the most important elementswith respect to the reliability of submicron CMOS ICs.

An NMOSFET is a very effective ESD protection device. Specifically, NMOSdevices, either with the gate grounded (GGNMOS) or with the gate coupledto the positive ESD transient voltage (GCNMOS), have been commonly usedas primary ESD protection elements for integrated circuits.

GGNMOS or GCNMOS can be used as the primary ESD protection element forESD protection of an input pin. The input pad is connected to the drainof the NMOS, whose gate is either grounded or coupled to the drain andVSS by a capacitor and a resistor. The drain of the NMOS transistor isthen connected to a series resistor of the order of 200 ohms, and then asecondary ESD protection element (say, a smaller GGNMOS) beforeconnected to the first input gate.

In one application, an NMOS is used as the pull down transistor of aCMOS buffer to drive an output voltage for an external device. In thistype of application, the gate of the NMOS is connected to an outputdriving signal.

In another common NMOS application, the gate is electrically connectedto ground, and the NMOS is used as an ESD protection device for an inputpin or a power bus during an ESD event.

The ESD protective action of an NMOS is based on the device's snap-backmechanism, which enables the NMOS to conduct a high level of ESD currentbetween its drain and source. This occurs when a strong electric fieldacross the depletion region in the drain substrate junction becomes highenough to begin avalanche breakdown, which in turn causes impactionization, resulting in the generation of both minority and majoritycarriers. The minority carriers flow toward the drain contact, and themajority carrier flow toward the substrate/p-well contact, causing alocal potential build up across the current path in the p-wellsubstrate.

When the local substrate potential is 0.6 V high than an adjacent n+source potential, the source junction becomes forward biased. Theforward biased source junction then injects minority carriers(electrons) into the p-well, and these carriers eventually reach thedrain junction to further enhance the impact ionization effect (see “ESDin Silicon Integrated Circuits”, by A. Amerasekera and C. Duvvury Chap.3, Sec. 1., John Wiley & Sons, 1995). Eventually, the NMOS reaches a lowimpedance (snap-back) state, which enables it to conduct a large amountof ESD current.

To enhance the ESD protection capabilities of a MOSFET device, it isdesirable to have a rapid turn on with a high degree of uniformitythroughout the device. A known technique for accomplishing thisobjective utilizes a multi-gate-finger configuration to increase thegate effectiveness. However, in a typical multi-gate-finger NMOSstructure, as shown in FIGS. 1 and 2, not all the poly gate fingers mayturn on during an ESD event. That is, when the first few gate fingersreach their snap-back low impedance mode, the drain terminal to sourceterminal voltage is reduced to a value, called the snap-back voltage,which is less than the trigger voltage of the NMOS device. This has theeffect of preventing the remaining gate fingers from being turned on. Asa result, only a partial number of the gate fingers are available toabsorb the ESD energy. Therefore, the ESD protection provided by theNMOS is significantly reduced.

When a MOSFET gate finger is triggered during an ESD event, the entirefinger turns on. This is due to the cascading effect of the previouslydescribed impact ionization and snap-back process along the entire gatefinger. Moreover, experimental data indicates that a long-gate-fingerstructure (e.g. 100 um×2), as shown in FIG. 4, has better ESDperformance than a short-gate-finger structure (e.g. 20 um×10), of thetype shown in FIG. 1, where both structures have the same total gatewidth of 200 um. That is, during an ESD event, the long-finger NMOSstructure will have either one or two gate fingers (50% to 100% of totalgate width) turned on, while the short-finger NMOS may only have a fewfingers (out of 10) turned on, with each finger being only 10% of thetotal gate width, thus reducing the short-finger MOSFET's ability toabsorb ESD current as compared to the long finger configuration. Formanufacturing purposes, however, layout area is typically at a premium,and a conventional long-finger structure may not fit in the designatedlayout area. Therefore, both multi-gate-finger (short) andlong-gate-finger (long) types of structures are used, depending onphysical and electrical priorities.

A commonly used multi-gate-finger structure is shown in FIG. 4, wherethe poly-gate fingers are connected by a poly-gate bus, rather than themetal bus of FIG. 1.

One prior art technique for improving the uniform turn on of such amulti-gage-finger NMOS structure uses a gate coupled technique, as shownin FIG. 5, and as described in “ESD in Silicon Integrated Circuits”, A.Amerasekera and C. Duvvury, Chap. 4, Sec. 2., John Wiley & Sons, 1995.In this configuration, the drain is connected to either VDD or thebuffer output line, and the gate is coupled to the drain via a capacitorC, and is also connected to ground via a resistor R. The couplingcapacitor C and the RC time constant of the circuit cause the gatepotential to rise to 1 to 2 V during the first 5 to 10 ns of an ESDevent. The positive gate voltage reduces the triggering threshold of theNMOS, thereby enabling a more uniform turn-on of the gate fingers.However, improving the uniformity of the turn-on state of each finger isdesirable.

SUMMARY OF THE INVENTION

The present invention overcomes the deficiencies of the prior art.Specifically, a dual-node capacitor coupling technique is used to lowerthe trigger voltage and to improve the uniform turn-on of a multi-fingerMOSFET transistor.

Preferably, each MOSFET is an NMOS device, although it will beunderstood by those skilled in the art that PMOS devices may be used asdesired. Each NMOS device includes a capacitor that is connected betweenthe gate of the NMOS device and the pad terminal. A first resistor isconnected between the gate and the p-well, while a second resistor isconnected between the p-well and the grounded source. For a positive ESDpulse to VSS, the p-well is pulled up to approximately 0.7 V during theinitial ESD event, such that the source junction is forward biased andthat the trigger voltage of the NMOS device is lowered. At the sametime, the gate voltage is coupled within the range of approximately 1 to2 V to promote the uniform turn on of the gate fingers of the NMOSdevices during the initial ESD event.

In another embodiment the input signal line from the pad terminal isreplaced by a VDD line from a VDD source to protect against a bus-to-busESD event, from VDD to VSS.

BRIEF DESCRIPTION OF THE DRAWINGS

The following detailed description, giving by way of example and notintended to limit the present invention solely thereto, will best beunderstood in conjunction with the accompanying drawings in which likereference numbers depict like elements:

FIG. 1 shows a conventional multi-gate-finger NMOS structure;

FIG. 2 is a schematic representation of the structure of FIG. 1;

FIG. 3 shows a conventional long-gate finger structure;

FIG. 4 depicts another conventional multi-gate-finger NMOS structure;

FIG. 5 is a schematic representation of a gate-coupled MOSFET;

FIG. 6 shows a dual-node capacitor in accordance with a first embodimentof the present invention;

FIG. 7 shows the inherent capacitor properties of the dual-nodecapacitor of FIG. 7 of the present invention; and

FIG. 8 shows a portion of a dual-node capacitor in accordance with asecond embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention improves over conventional gate-coupling andwell-coupling techniques in that the embodiments provide a lower triggervoltage for each MOSFET in the multi-finger MOSFET device, whileimproving the turn-on consistency for each MOSFET. Note that, althoughthe present invention is particularly well suited to a multi-fingerMOSFET ESD protection device, the present invention may also be employedin a single MOSFET device while providing stellar results.

FIG. 6 shows an ESD protection device 60 having a dual-node capacitor inaccordance with a first embodiment of the present invention. Protectiondevice 60 is positioned between an IC pad terminal 10 and a buffer 20that connects to an internal circuit (not shown) to be protected from anESD event.

Device 60 includes a primary protection circuit that includes MOSFET 40,capacitor 12, and first and second resistors 14, 16, respectively.Illustratively, MOSFET 40 is an NMOS transistor but as previouslydiscussed, may be a PMOS transistor as well. In addition, although onlyone NMOS transistor is shown, it is to be understood that multipletransistors may be connected in parallel, with their poly gatesconnected together to a capacitor and first and second resistors, toform a dual-node capacitor coupled multi-finger MOSFET device.Accordingly, the protection device of FIG. 6 preferably has amulti-finger structure.

Referring back to FIG. 6, capacitor 12 is connected between the gate ofNMOS device 40 and pad 10. First resistor 14 is connected between thegate and the p-well (or bulk), while second resistor 16 is connectedbetween the p-well and the grounded source (to VSS) of the NMOS. Inaddition, a resistor 18 is located between pad 10 and buffer 20.Further, an optional secondary ESD protection circuit, comprising asmaller NMOSFET 50, is included as well.

Note that if MOSFET device 40 was a PMOSFET (so that its bulk is formedof an n-well region), its drain would be connected between pad 10 andbuffer 20, and its source would be connected to power source VDD.

The basic operation of FIG. 6 will now be discussed. In particular, theunique structure of a single capacitor and two serially connectedresistors simultaneously pulls the p-well voltage potential, of eachNMOS in the multi-finger structure, to approximately 0.7 V. In addition,the gate voltage potential is pulled within the approximate range of 1to 2 V during the first 5 to 10 ns of the ESD event. As an example, theresistor ratio R₁R/R₂ is in the range of 0.2 to 5, and preferably in therange of 0.5 to 2.

As discussed, a 1 to 2 V gate potential assists in the uniform turn-onof NMOS fingers during an ESD event. An approximate 0.7 V p-wellpotential, during the initial ESD event, causes the source junction tobecome forward-biased such that minority carriers are injected which,when flowing towards the drain, help to reduce the trigger voltage ofthe snap-back mechanism so as to improve the ESD robustness of the NMOStransistor.

FIG. 7 shows the inherent parasitic capacitor properties of thedual-node capacitor of FIG. 6 of the present invention. Specifically,device 60 is now shown having parasitic capacitor 32 (ground-to-drain),34 (ground-to-bulk), 36 (source-to-bulk), 39 (gate-to-source), as wellas diode 38.

The operation of FIGS. 6 will now be discussed with greater detail withreference to FIG. 7. During the first 5 to 10 ns of an ESD event, thevoltage potential of the p-well (Vb) is pulled up and pinned at theforward-bias voltage (to approximately 0.7 V) of the p-well to n-sourcejunction diode. The gate potential (Vg) is pulled up to within the rangeof approximately 1 to 2 V due to the capacitor coupling 12, while thepad terminal 10 is around 1.5 to 20 V. The coupling ratio is determinedby the following equation:

(C_(c)+C_(GD))/(C_(GD)+C_(GS)+C_(GS)),   (1)

where C_(C) is the coupling capacitance between the drain and the gate,C_(GD) is the gate-to-drain overlap capacitance, C_(GS) is thegate-to-source overlap capacitance and C_(GB) is the gate-oxidecapacitance. The initial R-C relaxation time constant when the sourcejunction is pinned at forward biasing may be expressed by the followingequation:

R1*(C_(c)+C_(GD)+C_(GS)+C_(GS)),   (2)

which is preferably designed to be within the range of approximately 10to 30 ns. As an example, the coupling capacitor used in the order of 0.5to 3 PF, and R1 (resistor 14) and R2 (resistor 16) are in the order to 4to 20 Kohms.

FIG. 8 illustrates and alternative embodiment of the present invention.Specifically, the inventive primary ESD protection circuit 80 isemployed to protect against a bus-to-bus ESD event, from VDD to VSS.Accordingly, the input signal line from pad terminal 10 of FIG. 6 isreplaced by a VDD line from VDD source 30, as shown in FIG. 8.

Furthermore, the pad terminal 10 in FIG. 6 or the first power bus (VDD)in FIG. 8 can be deemed as a first stress node, and the second power bus(VSS) can be deemed as a second stress node. Since the gate of theMOSFET device 40 and the p-well (base) are coupled to the first stressat least by a first common element (e.g., the capacitor 12 ) and alsocoupled to the second stress node at least by a second common element(e.g., the resistor 16 ), during an ESD event, either the first andsecond stress node may see a high ESD voltage, and the first and secondstress nodes can bypass an ESD current when the ESD protection circuitis triggered to conduct a larger ESD transient current.

Finally, the above-discussion is intended to be merely illustrative ofthe invention. Numerous alternative embodiments may be devised by thosehaving ordinary skill in the art without departing from the spirit andscope of the following claims.

What is claimed is:
 1. An ESD protection circuit for lowering thetrigger voltage and improving the turn-on consistency of a MOSFETdevice, comprising: a MOSFET device having a source, a drain, a gate anda bulk; a capacitor connected the gate of said MOSFET and a padterminal; a first resistor connected between the gate and the bulk ofsaid MOSFET; and a second resistor connected between the bulk and apower bus.
 2. The circuit of claim 1, wherein said source is connectedto said power bus.
 3. The circuit of claim 1, wherein said MOSFET is aPMOSFET.
 4. The circuit of claim 3, wherein said power bus is VDD. 5.The circuit of claim 1, further comprising multiple MOSFET devicesconnected in parallel, wherein all gates of said multiple MOSFET devicesare electrically connected together.
 6. The circuit of claim 5, whereinat least two drains of said multiple MOSFET devices are electricallyconnected together.
 7. The circuit of claim 5, wherein at least twoMOSFET devices share a common drain diffusion region.
 8. The circuit ofclaim 5, wherein at least two sources of said multiple MOSFET devicesare electrically connected together.
 9. The circuit of claim 5, whereinat least two MOSFET devices share a common source diffusion region. 10.The circuit of claim 5, wherein said multiple MOSFET devices form amulti-finger structure.
 11. The circuit of claim 1, wherein said drainis connected between said pad and a buffer.
 12. The circuit of claim 11,wherein said bulk is a p-well, said p-well having a voltage potential ofapproximately 0.7 V, and said gate has a voltage potential approximatelyin the range of 1.0 to 2.0 V during as ESD event.
 13. The circuit ofclaim 1, wherein said MOSFET is an NMOSFET.
 14. The circuit of claim 13,wherein said power bus is a GND.
 15. The circuit of claim 1, furthercomprising a third resistor connected between said pad terminal and abuffer.
 16. The circuit of claim 15, further comprising a second MOSFETcoupled between said buffer and said power bus.
 17. An ESD protectioncircuit for lowering the trigger voltage and improving the turn-onconsistency of a MOSFET device, comprising: a MOSFET device having asource, a drain, a gate and a bulk; a capacitor connected between thegate of said MOSFET and a first power bus; a first resistor connectedbetween the gate and the bulk of said MOSFET; and second resistorconnected between the bulk and a second power bus.
 18. The circuit ofclaim 17, wherein said first power bus is a VDD bus and said secondpower bus is a VSS bus.
 19. The circuit of claim 17, wherein said firstpower bus is a VDD bus and said second power bus is GND.
 20. The circuitof claim 17, wherein said drain of said MOSFET is connected to saidfirst power bus and said source of said MOSFET is connected to saidsecond power bus.
 21. The circuit of claim 17, wherein said secondresistor is in series with said first resistor.
 22. An ESD protectionstructure, comprising: a MOSFET device comprising a source, a drain, agate and a body; a capacitor coupled between said gate and said drain; afirst resistor coupled between said gate and said body; and a secondresistor coupled between said body and said source.
 23. The circuit ofclaim 22, wherein said source is connected to a power bus.
 24. Thecircuit of claim 23, wherein said power bus is a GND.
 25. The circuit ofclaim 22, wherein said MOSFET is a PMOSFET.
 26. The circuit of claim 22,further comprising multiple MOSFET devices connected in parallel,wherein all gates of said multiple MOSFET devices are electricallyconnected together.
 27. The circuit of claim 26, wherein at least twodrains of said multiple MOSFET devices are electrically connectedtogether.
 28. The circuit of claim 26, wherein at least two MOSFETdevice share a common drain diffusion region.
 29. The circuit of claim26, wherein at least two sources of said multiple MOSFET devices areelectrically connected together.
 30. The circuit of claim 26, wherein atleast two MOSFET device share a common source diffusion region.
 31. Thecircuit of claim 26, wherein said multiple MOSFET devices form amulti-finger structure.
 32. The circuit of claim 22, wherein said drainis connected between a pad and a buffer.
 33. The circuit of claim 22,wherein said MOSFET is an NMOSFET.
 34. The circuit of claim 22, furthercomprising a third resistor connected between said drain and a buffer.35. An ESD protection circuit for an integrated circuit, comprising: aMOS transistor having a source node, a drain node, a gate node and abase node, wherein said gate node is coupled to a first node through acapacitor and is coupled to a second node through a first resistor,wherein said base node is coupled to the first node through saidcapacitor and is coupled to the second node through said first resistor,and wherein said first node is subject to electrostatic-discharge stressduring an ESD event.
 36. The circuit of claim 35, wherein said firstnode is coupled to said drain node.
 37. The circuit of claim 35, whereinsaid first node is coupled to a signal pad.
 38. The circuit of claim 35,wherein said first node is coupled to a first power bus.
 39. The circuitof claim 35, wherein said second node is coupled to said source node.40. The circuit of claim 35, wherein said second node is coupled to asecond power bus.
 41. The circuit of claim 35, wherein said MOStransistor is a NMOS transistor, said base node being a p-well, and saidsecond node being coupled to VSS.
 42. The circuit of claim 35, whereinsaid MOS transistor is a PMOS transistor, said base note being ann-well, and said second node being coupled to VDD.
 43. The circuit ofclaim 35, wherein said MOS transistor is a multi-gate-finger MOStransistor.
 44. The circuit of claim 35 further comprising anelectrically conducting element coupled between said gate node and saidbase node.
 45. The circuit of claim 44, wherein said electricallyconducting element is a second resistor.
 46. An ESD protection circuit,comprising: a MOS transistor having a source node, a drain node, a gatenode, and a base node, wherein said gate node is coupled to a first nodethrough a first impedance and is coupled to a second node through asecond impedance, wherein said base node is coupled to the first nodethrough said first impedance and is coupled to the second node throughsaid second impedance, and wherein said first node is subject toelectrostatic-discharge stress during an ESD event.
 47. The circuit ofclaim 46, wherein said first impedance comprises a capacitive element.48. The circuit of claim 46, wherein said first node is coupled to saiddrain node.
 49. The circuit of claim 46, wherein said first node iscoupled to a single pad.
 50. The circuit of claim 46, wherein said firstnode is coupled to a first power bus.
 51. The circuit of claim 46,wherein said second node is coupled to said source node.
 52. The circuitof claim 46, wherein said second node is coupled a second power bus. 53.The circuit of claim 46, wherein said MOS transistor is a NMOStransistor, said base region being a p-well, and said second node beingcoupled to ground.
 54. The circuit of claim 46, wherein said MOStransistor is a PMOS transistor, said base node being an n-well, andsaid second node being coupled to VDD.
 55. The circuit of claim 46,wherein said MOS transistor is a multi-gate-finger MOS transistor. 56.The circuit of claim 46, further comprising an electrically conductingelement coupled between said gate node and said base node.
 57. Thecircuit of claim 56, wherein said electrically conducting element is aresistor.